@inproceedings{63b53555a4804fbd90a2d1a35398c2f9,
title = "High-level specification and efficient implementation of pipelined circuits",
abstract = "This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modular specification language with an efficient implementation. In our system, the designer specifies the circuit as a set of independent modules connected by conceptually unbounded queues. Our synthesis algorithm automatically transforms this modular, asynchronous specification into a tightly coupled, fully synchronous implementation in synthesizable Verilog.",
keywords = "Circuit synthesis, Clocks, Computer science, Coupling circuits, Feedback circuits, Hardware design languages, Laboratories, Pipeline processing, Scheduling algorithm, Specification languages",
author = "Marinescu, {M. C.} and M. Rinard",
note = "Publisher Copyright: {\textcopyright} 2001 IEEE.; Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 ; Conference date: 30-01-2001 Through 02-02-2001",
year = "2001",
doi = "10.1109/ASPDAC.2001.913384",
language = "English",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "655--661",
booktitle = "Proceedings of the ASP-DAC 2001",
address = "United States",
}