An FPGA-based approach for parameter estimation in spiking neural networks

Horacio Rostro-Gonzalez, Guillaume Garreau, Andreas Andreou, Julius Georgiou, Jose H. Barron-Zambrano, Cesar Torres-Huitzil

Producción científica: Contribución a una conferenciaContribuciónrevisión exhaustiva

1 Cita (Scopus)

Resumen

We present an FPGA-based approach for estimating the delayed synaptic weights of spiking neural networks. Our approach makes explicit use of the fact that reverse engineering of a spiking neural network can be cast as a linear programming problem, whereby the objective function is based on the network spiking activity. The solution is obtained by employing the widely used simplex algorithm. Numerical results on a Xilinx Spartan 3 FPGA board show that the present approach can be used to reproduce a desired output from the observed network spiking activity.

Idioma originalInglés
Páginas2897-2900
Número de páginas4
DOI
EstadoPublicada - 2012
Publicado de forma externa
Evento2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, República de Corea
Duración: 20 may 201223 may 2012

Conferencia

Conferencia2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
País/TerritorioRepública de Corea
CiudadSeoul
Período20/05/1223/05/12

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