A synthesis algorithm for modular design of pipelined circuits

This paper presents a synthesis algorithm for pipelined circuits. The circuit is specified as a collection of independent loosely coupled modules connected by queues. The synthesis algorithm transforms this asynchronous, modular specification into a synchronous, tightly-coupled, curd fully pipelined circuit in which queues are implemented as finite buffers. Data is read from the buffers at the begining of each clock cycle, new values are computed, then the new results are written back into the buffers at the end of each clock cycle.We have implemented a prototype synthesizer that is capable of automatically generating synchronous, fully pipelined implementations of modular specifications. This paper presents experimental results from thin synthesizer.