8-bit gray-scale DTCNN implementation over an FPGA for robot guiding algorithm

J. Alb́o-Canals, Jose Á Villasante-Bembibre, Jordi Riera-Babuŕes, X. Vilasis-Cardona

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Resumen

This paper presents the application of an 8-bit Field Programmable Gate Array (FPGA) implementation of a Discrete Time Cellular Neural Network (DTCNN) suitable for small image gray-scale pre-processing (simple operations with high computational burden). It uses Split&Shift techniques to have a 12 × 12 grid. Reduced grid is necessary because of windowing process is added to process bigger images (NIOSII and peripherical elements occupation consume 4000 logic elements (LE) approximately). The implementation over the FPGA uses I 2C interfece to comunicate with Lego Mindstorm Device.

Idioma originalInglés
Título de la publicación alojada2010 12th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2010
EditorialIEEE Computer Society
ISBN (versión impresa)9781424466795
DOI
EstadoPublicada - 2010
Evento2010 12th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2010 - Berkeley, CA, Estados Unidos
Duración: 3 feb 20105 feb 2010

Serie de la publicación

Nombre2010 12th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2010

Conferencia

Conferencia2010 12th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2010
País/TerritorioEstados Unidos
CiudadBerkeley, CA
Período3/02/105/02/10

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