TY - GEN
T1 - 8-bit gray-scale DTCNN implementation over an FPGA for robot guiding algorithm
AU - Alb́o-Canals, J.
AU - Villasante-Bembibre, Jose Á
AU - Riera-Babuŕes, Jordi
AU - Vilasis-Cardona, X.
PY - 2010
Y1 - 2010
N2 - This paper presents the application of an 8-bit Field Programmable Gate Array (FPGA) implementation of a Discrete Time Cellular Neural Network (DTCNN) suitable for small image gray-scale pre-processing (simple operations with high computational burden). It uses Split&Shift techniques to have a 12 × 12 grid. Reduced grid is necessary because of windowing process is added to process bigger images (NIOSII and peripherical elements occupation consume 4000 logic elements (LE) approximately). The implementation over the FPGA uses I 2C interfece to comunicate with Lego Mindstorm Device.
AB - This paper presents the application of an 8-bit Field Programmable Gate Array (FPGA) implementation of a Discrete Time Cellular Neural Network (DTCNN) suitable for small image gray-scale pre-processing (simple operations with high computational burden). It uses Split&Shift techniques to have a 12 × 12 grid. Reduced grid is necessary because of windowing process is added to process bigger images (NIOSII and peripherical elements occupation consume 4000 logic elements (LE) approximately). The implementation over the FPGA uses I 2C interfece to comunicate with Lego Mindstorm Device.
UR - http://www.scopus.com/inward/record.url?scp=77952402494&partnerID=8YFLogxK
U2 - 10.1109/cnna.2010.5430336
DO - 10.1109/cnna.2010.5430336
M3 - Conference contribution
AN - SCOPUS:77952402494
SN - 9781424466795
T3 - 2010 12th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2010
BT - 2010 12th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2010
PB - IEEE Computer Society
T2 - 2010 12th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2010
Y2 - 3 February 2010 through 5 February 2010
ER -