Radiation hard programmable delay line for LHCb calorimeter upgrade

J. Mauricio, D. Gascón, X. Vilasís, E. Picatoste, F. MacHefert, J. Lefrancois, O. Duarte, C. Beigbeder

Research output: Indexed journal article Articlepeer-review

2 Citations (Scopus)


This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with less than 5 ps jitter and 23 ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end analog signal processing ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise contribution of digital components. This is accomplished by implementing the DLL in differential mode. To achieve the required radiation tolerance several techniques are applied: double guard rings between PMOS and NMOS transistors as well as glitch suppressors and TMR Registers. This 5.7 mm2 chip has been implemented in CMOS 0.35 μm technology.

Original languageEnglish
Article numberC01016
JournalJournal of Instrumentation
Issue number1
Publication statusPublished - Jan 2014


  • Front-end electronics for detector readout
  • Radiation-hard electronics
  • VLSI circuits


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