High-level synthesis of pipelined circuits from modular queue-based specifications

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This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modular specification language with an efficient implementation. In our system, the designer specifies the circuit as a set of independent modules connected by conceptually unbounded queues. Our synthesis algorithm automatically transforms this modular, asynchronous specification into a tightly coupled, fully synchronous implementation in synthesizable Verilog.

Original languageEnglish
Pages (from-to)2655-2664
Number of pages10
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number11
Publication statusPublished - Nov 2001
Externally publishedYes


  • Asynchronous
  • Modular
  • Pipeline
  • Term rewriting system


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