High-level specification and efficient implementation of pipelined circuits

M. C. Marinescu; M. Rinard

doi:10.1109/ASPDAC.2001.913384

High-level specification and efficient implementation of pipelined circuits

M. C. Marinescu, M. Rinard

Research output: Book chapter › Conference contribution › peer-review

5 Citations (Scopus)

Abstract

This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modular specification language with an efficient implementation. In our system, the designer specifies the circuit as a set of independent modules connected by conceptually unbounded queues. Our synthesis algorithm automatically transforms this modular, asynchronous specification into a tightly coupled, fully synchronous implementation in synthesizable Verilog.

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2001
Subtitle of host publication	Asia and South Pacific Design Automation Conference 2001
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	655-661
Number of pages	7
ISBN (Electronic)	0780366336
DOIs	https://doi.org/10.1109/ASPDAC.2001.913384
Publication status	Published - 2001
Externally published	Yes
Event	Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 - Yokohama, Japan Duration: 30 Jan 2001 → 2 Feb 2001

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	2001-January

Conference

Conference	Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001
Country/Territory	Japan
City	Yokohama
Period	30/01/01 → 2/02/01

Keywords

Circuit synthesis
Clocks
Computer science
Coupling circuits
Feedback circuits
Hardware design languages
Laboratories
Pipeline processing
Scheduling algorithm
Specification languages

Access to Document

10.1109/ASPDAC.2001.913384

Cite this

Marinescu, M. C., & Rinard, M. (2001). High-level specification and efficient implementation of pipelined circuits. In Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001 (pp. 655-661). Article 913384 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2001-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2001.913384

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abstract = "This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modular specification language with an efficient implementation. In our system, the designer specifies the circuit as a set of independent modules connected by conceptually unbounded queues. Our synthesis algorithm automatically transforms this modular, asynchronous specification into a tightly coupled, fully synchronous implementation in synthesizable Verilog.",

keywords = "Circuit synthesis, Clocks, Computer science, Coupling circuits, Feedback circuits, Hardware design languages, Laboratories, Pipeline processing, Scheduling algorithm, Specification languages",

author = "Marinescu, {M. C.} and M. Rinard",

note = "Publisher Copyright: {\textcopyright} 2001 IEEE.; Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 ; Conference date: 30-01-2001 Through 02-02-2001",

year = "2001",

doi = "10.1109/ASPDAC.2001.913384",

language = "English",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

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Marinescu, MC & Rinard, M 2001, High-level specification and efficient implementation of pipelined circuits. in Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001., 913384, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2001-January, Institute of Electrical and Electronics Engineers Inc., pp. 655-661, Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001, Yokohama, Japan, 30/01/01. https://doi.org/10.1109/ASPDAC.2001.913384

High-level specification and efficient implementation of pipelined circuits. / Marinescu, M. C.; Rinard, M.
Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., 2001. p. 655-661 913384 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2001-January).

Research output: Book chapter › Conference contribution › peer-review

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KW - Hardware design languages

KW - Laboratories

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Marinescu MC, Rinard M. High-level specification and efficient implementation of pipelined circuits. In Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc. 2001. p. 655-661. 913384. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.2001.913384

High-level specification and efficient implementation of pipelined circuits

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Publication series

Conference

Keywords

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