An FPGA-based approach for parameter estimation in spiking neural networks

Horacio Rostro-Gonzalez; Guillaume Garreau; Andreas Andreou; Julius Georgiou; Jose H. Barron-Zambrano; Cesar Torres-Huitzil

doi:10.1109/ISCAS.2012.6271920

An FPGA-based approach for parameter estimation in spiking neural networks

Horacio Rostro-Gonzalez^*
, Guillaume Garreau
, Andreas Andreou
, Julius Georgiou
, Jose H. Barron-Zambrano
, Cesar Torres-Huitzil

^*Corresponding author for this work

Research output: Conference paper › Contribution › peer-review

1 Citation (Scopus)

Abstract

We present an FPGA-based approach for estimating the delayed synaptic weights of spiking neural networks. Our approach makes explicit use of the fact that reverse engineering of a spiking neural network can be cast as a linear programming problem, whereby the objective function is based on the network spiking activity. The solution is obtained by employing the widely used simplex algorithm. Numerical results on a Xilinx Spartan 3 FPGA board show that the present approach can be used to reproduce a desired output from the observed network spiking activity.

Original language	English
Pages	2897-2900
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271920
Publication status	Published - 2012
Externally published	Yes
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 20 May 2012 → 23 May 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/Territory	Korea, Republic of
City	Seoul
Period	20/05/12 → 23/05/12

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10.1109/ISCAS.2012.6271920

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title = "An FPGA-based approach for parameter estimation in spiking neural networks",

abstract = "We present an FPGA-based approach for estimating the delayed synaptic weights of spiking neural networks. Our approach makes explicit use of the fact that reverse engineering of a spiking neural network can be cast as a linear programming problem, whereby the objective function is based on the network spiking activity. The solution is obtained by employing the widely used simplex algorithm. Numerical results on a Xilinx Spartan 3 FPGA board show that the present approach can be used to reproduce a desired output from the observed network spiking activity.",

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year = "2012",

doi = "10.1109/ISCAS.2012.6271920",

language = "English",

pages = "2897--2900",

note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

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Rostro-Gonzalez, H, Garreau, G, Andreou, A, Georgiou, J, Barron-Zambrano, JH & Torres-Huitzil, C 2012, 'An FPGA-based approach for parameter estimation in spiking neural networks', Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of, 20/05/12 - 23/05/12 pp. 2897-2900. https://doi.org/10.1109/ISCAS.2012.6271920

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AU - Rostro-Gonzalez, Horacio

AU - Garreau, Guillaume

AU - Andreou, Andreas

AU - Georgiou, Julius

AU - Barron-Zambrano, Jose H.

AU - Torres-Huitzil, Cesar

PY - 2012

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AB - We present an FPGA-based approach for estimating the delayed synaptic weights of spiking neural networks. Our approach makes explicit use of the fact that reverse engineering of a spiking neural network can be cast as a linear programming problem, whereby the objective function is based on the network spiking activity. The solution is obtained by employing the widely used simplex algorithm. Numerical results on a Xilinx Spartan 3 FPGA board show that the present approach can be used to reproduce a desired output from the observed network spiking activity.

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An FPGA-based approach for parameter estimation in spiking neural networks

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