An FPGA-based approach for parameter estimation in spiking neural networks

Horacio Rostro-Gonzalez, Guillaume Garreau, Andreas Andreou, Julius Georgiou, Jose H. Barron-Zambrano, Cesar Torres-Huitzil

Research output: Conference paperContributionpeer-review

1 Citation (Scopus)

Abstract

We present an FPGA-based approach for estimating the delayed synaptic weights of spiking neural networks. Our approach makes explicit use of the fact that reverse engineering of a spiking neural network can be cast as a linear programming problem, whereby the objective function is based on the network spiking activity. The solution is obtained by employing the widely used simplex algorithm. Numerical results on a Xilinx Spartan 3 FPGA board show that the present approach can be used to reproduce a desired output from the observed network spiking activity.

Original languageEnglish
Pages2897-2900
Number of pages4
DOIs
Publication statusPublished - 2012
Externally publishedYes
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 20 May 201223 May 2012

Conference

Conference2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/TerritoryKorea, Republic of
CitySeoul
Period20/05/1223/05/12

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