A synthesis algorithm for modular design of pipelined circuits

MC Marinescu; M Rinard

doi:10.1007/978-0-387-35498-9_53

A synthesis algorithm for modular design of pipelined circuits

Research output: Book chapter › Conference contribution › peer-review

Abstract

This paper presents a synthesis algorithm for pipelined circuits. The circuit is specified as a collection of independent loosely coupled modules connected by queues. The synthesis algorithm transforms this asynchronous, modular specification into a synchronous, tightly-coupled, curd fully pipelined circuit in which queues are implemented as finite buffers. Data is read from the buffers at the begining of each clock cycle, new values are computed, then the new results are written back into the buffers at the end of each clock cycle.We have implemented a prototype synthesizer that is capable of automatically generating synchronous, fully pipelined implementations of modular specifications. This paper presents experimental results from thin synthesizer.

Original language	English
Title of host publication	Vlsi: Systems On A Chip
Editors	LM Silveira, S Devadas, R Reis
Publisher	Kluwer Academic Publishers
Pages	620-635
Number of pages	16
Volume	34
ISBN (Print)	0-7923-7731-1
DOIs	https://doi.org/10.1007/978-0-387-35498-9_53
Publication status	Published - 2000
Externally published	Yes
Event	IFIP 10th International Conference on Very Large Scale Integration (VLSI 99) - LISBON, Portugal Duration: 1 Dec 1999 → 4 Dec 1999

Publication series

Name	International Federation For Information Processing

Conference

Conference	IFIP 10th International Conference on Very Large Scale Integration (VLSI 99)
Country/Territory	Portugal
City	LISBON
Period	1/12/99 → 4/12/99

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10.1007/978-0-387-35498-9_53

Cite this

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title = "A synthesis algorithm for modular design of pipelined circuits",

abstract = "This paper presents a synthesis algorithm for pipelined circuits. The circuit is specified as a collection of independent loosely coupled modules connected by queues. The synthesis algorithm transforms this asynchronous, modular specification into a synchronous, tightly-coupled, curd fully pipelined circuit in which queues are implemented as finite buffers. Data is read from the buffers at the begining of each clock cycle, new values are computed, then the new results are written back into the buffers at the end of each clock cycle.We have implemented a prototype synthesizer that is capable of automatically generating synchronous, fully pipelined implementations of modular specifications. This paper presents experimental results from thin synthesizer.",

author = "MC Marinescu and M Rinard",

year = "2000",

doi = "10.1007/978-0-387-35498-9_53",

language = "English",

isbn = "0-7923-7731-1",

volume = "34",

series = "International Federation For Information Processing",

publisher = "Kluwer Academic Publishers",

pages = "620--635",

editor = "LM Silveira and S Devadas and R Reis",

booktitle = "Vlsi: Systems On A Chip",

address = "Netherlands",

note = "IFIP 10th International Conference on Very Large Scale Integration (VLSI 99) ; Conference date: 01-12-1999 Through 04-12-1999",

}

Marinescu, MC & Rinard, M 2000, A synthesis algorithm for modular design of pipelined circuits. in LM Silveira, S Devadas & R Reis (eds), Vlsi: Systems On A Chip. vol. 34, International Federation For Information Processing, Kluwer Academic Publishers, pp. 620-635, IFIP 10th International Conference on Very Large Scale Integration (VLSI 99), LISBON, Portugal, 1/12/99. https://doi.org/10.1007/978-0-387-35498-9_53

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ER -

A synthesis algorithm for modular design of pipelined circuits

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