8-bit gray-scale DTCNN implementation over an FPGA for robot guiding algorithm

J. Alb́o-Canals, Jose Á Villasante-Bembibre, Jordi Riera-Babuŕes, X. Vilasis-Cardona

Research output: Book chapterConference contributionpeer-review

1 Citation (Scopus)

Abstract

This paper presents the application of an 8-bit Field Programmable Gate Array (FPGA) implementation of a Discrete Time Cellular Neural Network (DTCNN) suitable for small image gray-scale pre-processing (simple operations with high computational burden). It uses Split&Shift techniques to have a 12 × 12 grid. Reduced grid is necessary because of windowing process is added to process bigger images (NIOSII and peripherical elements occupation consume 4000 logic elements (LE) approximately). The implementation over the FPGA uses I 2C interfece to comunicate with Lego Mindstorm Device.

Original languageEnglish
Title of host publication2010 12th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2010
PublisherIEEE Computer Society
ISBN (Print)9781424466795
DOIs
Publication statusPublished - 2010
Event2010 12th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2010 - Berkeley, CA, United States
Duration: 3 Feb 20105 Feb 2010

Publication series

Name2010 12th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2010

Conference

Conference2010 12th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2010
Country/TerritoryUnited States
CityBerkeley, CA
Period3/02/105/02/10

Fingerprint

Dive into the research topics of '8-bit gray-scale DTCNN implementation over an FPGA for robot guiding algorithm'. Together they form a unique fingerprint.

Cite this