TY - JOUR
T1 - An FPGA scalable software defined radio platform design for educational and research purposes
AU - Hervás, Marcos
AU - Alsina-Pagès, Rosa Ma
AU - Salvador, Martí
N1 - Publisher Copyright:
© 2016 by the authors; licensee MDPI, Basel, Switzerland.
PY - 2016/6/1
Y1 - 2016/6/1
N2 - In a digital modem design, the integration of the Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC) with the core processor is usually a major issue for the designer. In this paper an FPGA scalable Software Defined Radio platform based on a Spartan-6 as a control unit is presented, developed for both educational and research purposes, which can fit the different application requirements in terms of analog front-end performance, processing unit and cost. The resolution and sampling frequency of the analog front-end are its main adjustable parameters. The processing core requirements involve the FPGA and the communication ports. A multidisciplinary working group was required to design a high performance system for both analog front-end and digital processing core in terms of signal integrity and electromagnetic compatibility. The platform has 5 different peripheral ports ranging from 16 kbps to 2.5 Gbps. The communication ports allow our students to develop a high range of applications for both on-site and online courses applying teaching methodology based on learning by doing using a real system to help them to reach other transversal skills.
AB - In a digital modem design, the integration of the Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC) with the core processor is usually a major issue for the designer. In this paper an FPGA scalable Software Defined Radio platform based on a Spartan-6 as a control unit is presented, developed for both educational and research purposes, which can fit the different application requirements in terms of analog front-end performance, processing unit and cost. The resolution and sampling frequency of the analog front-end are its main adjustable parameters. The processing core requirements involve the FPGA and the communication ports. A multidisciplinary working group was required to design a high performance system for both analog front-end and digital processing core in terms of signal integrity and electromagnetic compatibility. The platform has 5 different peripheral ports ranging from 16 kbps to 2.5 Gbps. The communication ports allow our students to develop a high range of applications for both on-site and online courses applying teaching methodology based on learning by doing using a real system to help them to reach other transversal skills.
KW - Educational platform
KW - Electromagnetic Compatibility (EMC)
KW - Field Programable Gate Array (FPGA)
KW - Programable logic
KW - Signal integrity
KW - Software Defined Radio (SDR)
UR - http://www.scopus.com/inward/record.url?scp=84973890109&partnerID=8YFLogxK
U2 - 10.3390/electronics5020027
DO - 10.3390/electronics5020027
M3 - Article
AN - SCOPUS:84973890109
SN - 2079-9292
VL - 5
JO - Electronics (Switzerland)
JF - Electronics (Switzerland)
IS - 2
M1 - 27
ER -