An FPGA-based approach for parameter estimation in spiking neural networks

Horacio Rostro-Gonzalez; Guillaume Garreau; Andreas Andreou; Julius Georgiou; Jose H. Barron-Zambrano; Cesar Torres-Huitzil

doi:10.1109/ISCAS.2012.6271920

An FPGA-based approach for parameter estimation in spiking neural networks

Horacio Rostro-Gonzalez, Guillaume Garreau, Andreas Andreou, Julius Georgiou, Jose H. Barron-Zambrano, Cesar Torres-Huitzil

Producció científica: Contribució a una conferència › Contribució › Avaluat per experts

1 Citació (Scopus)

Resum

We present an FPGA-based approach for estimating the delayed synaptic weights of spiking neural networks. Our approach makes explicit use of the fact that reverse engineering of a spiking neural network can be cast as a linear programming problem, whereby the objective function is based on the network spiking activity. The solution is obtained by employing the widely used simplex algorithm. Numerical results on a Xilinx Spartan 3 FPGA board show that the present approach can be used to reproduce a desired output from the observed network spiking activity.

Idioma original	Anglès
Pàgines	2897-2900
Nombre de pàgines	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271920
Estat de la publicació	Publicada - 2012
Publicat externament	Sí
Esdeveniment	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Durada: 20 de maig 2012 → 23 de maig 2012

Conferència

Conferència	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
País/Territori	Korea, Republic of
Ciutat	Seoul
Període	20/05/12 → 23/05/12

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10.1109/ISCAS.2012.6271920

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@conference{f98b0508c49042578508562de539f8f3,

title = "An FPGA-based approach for parameter estimation in spiking neural networks",

abstract = "We present an FPGA-based approach for estimating the delayed synaptic weights of spiking neural networks. Our approach makes explicit use of the fact that reverse engineering of a spiking neural network can be cast as a linear programming problem, whereby the objective function is based on the network spiking activity. The solution is obtained by employing the widely used simplex algorithm. Numerical results on a Xilinx Spartan 3 FPGA board show that the present approach can be used to reproduce a desired output from the observed network spiking activity.",

author = "Horacio Rostro-Gonzalez and Guillaume Garreau and Andreas Andreou and Julius Georgiou and Barron-Zambrano, {Jose H.} and Cesar Torres-Huitzil",

year = "2012",

doi = "10.1109/ISCAS.2012.6271920",

language = "English",

pages = "2897--2900",

note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

}

Rostro-Gonzalez, H, Garreau, G, Andreou, A, Georgiou, J, Barron-Zambrano, JH & Torres-Huitzil, C 2012, 'An FPGA-based approach for parameter estimation in spiking neural networks', Paper presentat a 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of, 20/05/12 - 23/05/12 pàg. 2897-2900. https://doi.org/10.1109/ISCAS.2012.6271920

An FPGA-based approach for parameter estimation in spiking neural networks. / Rostro-Gonzalez, Horacio; Garreau, Guillaume; Andreou, Andreas et al.
2012. 2897-2900 Paper presentat a 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of.

Producció científica: Contribució a una conferència › Contribució › Avaluat per experts

TY - CONF

T1 - An FPGA-based approach for parameter estimation in spiking neural networks

AU - Rostro-Gonzalez, Horacio

AU - Garreau, Guillaume

AU - Andreou, Andreas

AU - Georgiou, Julius

AU - Barron-Zambrano, Jose H.

AU - Torres-Huitzil, Cesar

PY - 2012

Y1 - 2012

N2 - We present an FPGA-based approach for estimating the delayed synaptic weights of spiking neural networks. Our approach makes explicit use of the fact that reverse engineering of a spiking neural network can be cast as a linear programming problem, whereby the objective function is based on the network spiking activity. The solution is obtained by employing the widely used simplex algorithm. Numerical results on a Xilinx Spartan 3 FPGA board show that the present approach can be used to reproduce a desired output from the observed network spiking activity.

AB - We present an FPGA-based approach for estimating the delayed synaptic weights of spiking neural networks. Our approach makes explicit use of the fact that reverse engineering of a spiking neural network can be cast as a linear programming problem, whereby the objective function is based on the network spiking activity. The solution is obtained by employing the widely used simplex algorithm. Numerical results on a Xilinx Spartan 3 FPGA board show that the present approach can be used to reproduce a desired output from the observed network spiking activity.

UR - http://www.scopus.com/inward/record.url?scp=84866596213&partnerID=8YFLogxK

UR - https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=pure_univeritat_ramon_llull&SrcAuth=WosAPI&KeyUT=WOS:000316903703024&DestLinkType=FullRecord&DestApp=WOS_CPL

U2 - 10.1109/ISCAS.2012.6271920

DO - 10.1109/ISCAS.2012.6271920

M3 - Contribution

AN - SCOPUS:84866596213

SP - 2897

EP - 2900

T2 - 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012

Y2 - 20 May 2012 through 23 May 2012

ER -

An FPGA-based approach for parameter estimation in spiking neural networks

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